Design of Adiabatic Logic Based Comparator for Low Power and High Speed Applications

This paper presents a novel modified comparator based on the combination of 2N-2N2P adiabatic logic and two phase adiabatic static clocked logic (2N-2N2P and 2PASCL), combination of efficient charge recovery adiabatic logic and two phase adiabatic static clocked logic (ECRL and 2PASCL). This new structure computes a decision making signal faster than the existing methods. The introduced logic based comparator demonstrates that the usage of high speed decision making signal allows high speed comparator, saving 60-80% of power in comparison with existing renowned conventional comparators. Adiabatic logic based circuit carry out less power consumption by constraining current flowing through devices with less voltage drop and by reusing the energy stored at output node instead of discharging it to ground. The design is simulated using Cadence Virtuoso Environment.